A programmable resistive device is generally referred to a device with a resistance state that may change by means of programming. Resistance states can also be determined by resistance values. For example, a resistive device can be a One-Time Programmable (OTP) device, such as electrical fuse, and the programming means can apply a high voltage to induce a high current to flow through the OTP element. When a high current flows through an OTP element by turning on a program selector, the OTP element can be programmed, or burned into a high or low resistance state (depending on either fuse or anti-fuse).
An electrical fuse is a common OTP element which is a programmable resistive device that can be constructed from a segment of interconnect, such as polysilicon, silicided polysilicon, silicide, metal, metal alloy, or some combination thereof. The metal can be aluminum, copper, or other transition metals. One commonly used electrical fuse is a CMOS gate, fabricated in silicided polysilicon, used as an interconnect. The electrical fuse can also be one or more contacts or vias instead of a segment of interconnect. A high current may blow the contact(s) or via(s) into a very high resistance state. The electrical fuse can be an anti-fuse, where a high voltage makes the resistance lower, instead of higher. The anti-fuse can consist of one or more contacts or vias with an insulator in between. The anti-fuse can also be a CMOS gate coupled to a CMOS body with a thin gate oxide as insulator.
A programmable resistive device can be a reversible resistive device that can be programmed into a digital logic value “0” or “1” repetitively and reversibly. The programmable resistive device can be fabricated from phase change material, such as Germanium (Ge), Antimony (Sb), and Tellurium (Te) with composition Ge2Sb2Te5 (GST-225) or GeSbTe-like materials including compositions of Indium (In), Tin (Sn), or Selenium (Se). Another phase change material can include a chalcogenide material such as AgInSbTe. The phase change material can be programmed into a high resistance amorphous state or a low resistance crystalline state by applying a short and high voltage pulse or a long and low voltage pulse, respectively.
Another type of reversible resistive device is a class of memory called Resistive RAM (RRAM), which is a normally insulating dielectric, but can be made conducting through filament, defects, metal migration, etc. The dielectric can be binary transition metal oxides such as NiO or TiO2, perovskite materials such as Sr(Zr)TiO3 or PCMO, organic charge transfer complexes such as CuTCNQ, or organic donor-acceptor systems such as Al AIDCN. As an example, RRAM can have cells fabricated from metal oxides between electrodes, such as Pt/NiO/Pt, TiN/TiOx/HfO2/TiN, TiN/ZnO/Pt, or W/TiN/SiO2/Si, etc. The resistance states can be changed reversibly and determined by polarity, magnitude, duration, voltage/current-limit, or the combinations thereof to generate or annihilate conductive filaments. Another programmable resistive device similar to RRAM is a Conductive Bridge RAM (CBRAM) that is based on electro-chemical deposition and removal of metal ions in a thin solid-state electrolyte film. The electrodes can be an oxidizable anode and an inert cathode and the electrolyte can be Ag- or Cu-doped chalcogenide glass such as GeSe, Cu2S, or GeS, etc. The resistance states can be changed reversibly and determined by polarity, magnitude, duration, voltage/current-limit, or combinations thereof to generate or annihilate conductive bridges. The programmable resistive device can also be an MRAM (Magnetic RAM) with cells fabricated from magnetic multi-layer stacks that construct a Magnetic Tunnel Junction (MTJ). In a Spin Transfer Torque MRAM (STT-MRAM) the direction of currents applied to an MTJ determines parallel or anti-parallel states, and hence low or high resistance states.
A conventional programmable resistive memory cell 10 is shown in FIG. 1(a). The cell 10 consists of a Programmable Resistive Element (PRE) 11 and an NMOS program selector 12. The resistive element 11 is coupled to the drain of the NMOS 12 at one end, and coupled to a high voltage V+ at the other end. The gate of the NMOS 12 is coupled to a select signal (Sel), and the source is coupled to a low voltage V−. When a high voltage is applied to V+ and a low voltage to V−, the resistive cell 10 can be programmed by raising the select signal (Sel) to turn on the NMOS 12. One of the most common resistive elements is a silicided polysilicon, the same material and fabricated at the same time as a MOS gate. The size of the NMOS 12, as program selector, needs to be large enough to deliver the required program current for a few microseconds. The program current for a silicided polysilicon is normally between a few milliamps for a fuse with width of 40 nm to about 20 mA for a fuse with width about 0.6 um. As a result, the cell size of an electrical fuse using silicided polysilicon tends to be very large. The resistive cell 10 can be organized as a two-dimensional array with all Sel's and V−'s in a row coupled as wordlines (WLs) and a ground line, respectively, and all V+'s in a column coupled as bitlines (BLs).
Another programmable resistive device 20 is shown in FIG. 1(b). The programmable resistive cell 20 has a Programmable Resistive Element (PRE) 21 and a diode as selector 22. The PRE 21 is coupled between an anode of the diode 22 and a high voltage V+. A cathode of the diode 22 is coupled to a low voltage V−. By applying a proper voltage between V+ and V− for a proper duration of time, the PRE 21 can be programmed into high or low resistance states, depending on voltage and duration. The programmable resistive cell 20 can be organized as a two dimensional array with all V−'s in a row coupled as wordline bars (WLBs), and all V+'s in a column coupled as bitlines (BLs).
FIG. 1(c) shows one embodiment of a conventional MRAM cell 310 using diodes 317 and 318 as program selectors in accordance with one embodiment. The MRAM cell 310 in FIG. 1(c) is a three-terminal MRAM cell. The MRAM cell 310 has an MTJ 311, including a free layer stack 312, a fixed layer stack 313, and a dielectric film 319 in between, and the two diodes 317 and 318. The free layer stack 312 is coupled to a supply voltage V, and coupled to the fixed layer stack 313 the dielectric film 319 which can be through a metal oxide such as Al2O3 or MgO. The diode 317 has the N terminal coupled to the fixed layer stack 313 and the P terminal coupled to V+ for programming a 1. The diode 318 has the P terminal coupled to the fixed layer stack 313 and the N terminal coupled to V− for programming a 0. If V+ voltage is higher than V, a current flows from V+ to V to program the MTJ 311 into state 1. Similarly, if V− voltage is lower than V, a current flows from V to V− to program the MTJ 311 into state 0. During programming, the other diode is supposedly cutoff. For reading, V+ and V− can be both set to 0V and the resistance between node V and V+/V− can be sensed to determine whether the MTJ 311 is in state 0 or 1. The cathode of diode 318 can be coupled to the anode of the diode 317 to constitute a two-terminal MRAM cell in another embodiment.
FIG. 2 shows a conventional 3D structure of anti-fuse cells built in a pillar of a cross-over between two layers of conductors in a vertical structure. See S. B. Herner et al, “Vertical p-i-n Polysilicon Diode with Anti-fuse for Stackable Field-Programmable ROM,” IEEE Elec. Dev. Lett. Vol. 25, No. 5, May, 2004. There are three layers of conductors running in approximately perpendicular directions. A pillar is built at a cross-over of two adjacent conductors. A p-i-n diode and a thin dielectric film of SiO2 are built inside the pillar to act as an anti-fuse. The fabrication processes involve building very complicated p-i-n diodes, dielectric stacks, and patterning. Special metals such as Tungsten are used in each layer of the conductors. The processing technology is quite different from the standard logic process. Moreover, the anti-fuse requires very high program voltage with large current to breakdown dielectrics, has wide post-program resistance distribution, and sometimes has reliability issues. In the advanced CMOS technologies beyond 40 nm, the nanometer devices cannot sustain voltage higher than 4.0V, not to mention about requiring large areas to build high voltage devices and charge pumps.
Therefore, there is a need for an invention to build high density programmable resistive devices that provide improved coupling between Programmable Resistive Devices (PRDs) with more reliability, lower voltage, and more CMOS compatible processes.